Dynamic Padding: 200 QPS with Zero Compute Waste for Short Audio
Why Whisper wastes 90% of compute on padding for 1-second commands, and how dynamic padding eliminates it.
asr performance concurrency systems deep-dive
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深入硬件架构、EDA 自动化与系统工程。 Deep dives into Hardware Architecture, EDA Automation, and Systems Engineering. 하드웨어 아키텍처, EDA 자동화 및 시스템 엔지니어링에 대한 심층 분석. 深入硬體架構、EDA 自動化與系統工程。
Dynamic Tensor Chunking: Constant 883MB Memory for Arbitrary-Length Audio
How slicing audio into 30-second tensor chunks prevents OOM on 24-hour recordings while keeping peak memory constant at 883MB.
asr memory systems rust deep-dive
RV32M Multiply/Divide Unit: 3-Cycle Mul, 32-Cycle Div
A multi-cycle RV32M unit implementing pipelined 33×33-bit multiplication (3 cycles) and restoring division with sign correction (32 cycles) — handling divide-by-zero and INT_MIN overflow edge cases.
risc-v mul-div arithmetic deep-dive
Heterogeneous Backend: Python + Rust MLX Architecture for ASR
Why Rust for compute and Python for orchestration, how they communicate, and how this split achieves 76ms TTFT.
asr rust python architecture deep-dive
BTB Branch Prediction for a Pipelined RISC-V CPU
Designing a 32-entry direct-mapped Branch Target Buffer for a 5-stage RISC-V pipeline — with tag comparison, train-on-taken update policy, and IF-stage bubble handling.
risc-v branch-prediction btb deep-dive
Local ASR Engine Deployment & Systems Optimization
A heterogeneous Rust+Python speech recognition engine achieving 76ms TTFT, constant 883MB memory, and 200 QPS on Apple Silicon.
project asr rust python systems
Data Hazard Resolution in a 5-Stage RISC-V Pipeline: Forwarding & Stall
Implementing dual-path data forwarding (MEM→EX, WB→EX) and load-use hazard detection with single-cycle stall in a pipelined RISC-V processor.
risc-v pipeline hazard forwarding deep-dive
Using LLM Agents to Explore EDA Synthesis Search Spaces
Why the hard part isn't the LLM — it's building a bulletproof engineering layer that catches hallucinations, prevents cyclic graphs, and rolls back failed mutations.
eda llm agent systems-engineering
Building a 5-Stage Pipelined RISC-V CPU in SystemVerilog
A complete RV32IM pipelined processor with BTB branch prediction, dual-path data forwarding, hazard detection, CSR support, and multi-cycle multiply/divide — synthesized on Xilinx Kintex-7 xc7k325t with WNS 0.048ns.
risc-v cpu systemverilog pipeline project
Porting Linux to RISC-V: Building a 64-bit System from Scratch on QEMU
Cross-compiling a RISC-V 64-bit Linux kernel with BusyBox rootfs, running on QEMU — from toolchain setup to shell prompt.
risc-v linux systems qemu deep-dive
SM4 Side-Channel Defence: LFSR Masking + Composite Field S-box
Designing DPA/EMA countermeasures for SM4: LFSR-based randomization, dual S-box architecture (LUT vs GF((2^4)^2)), and 3-level security control — with avalanche effect at 50.1%.
fpga crypto security side-channel deep-dive
SM4 32-Stage Pipeline: From 50MHz to 94MHz Timing Closure
How Active Bypass, EDA retiming, and progressive SDC constraints took a 32-stage SM4 crypto pipeline from -6.5ns setup violation to 94.19MHz Fmax on Cyclone V.
fpga crypto verilog timing deep-dive
Bit-Parallel Simulation: 15× Faster Equivalence Checking with 64-bit Wordwise Operations
How packing 64 simulation vectors into a single CPU register eliminates the per-vector loop and achieves cache-friendly sequential memory access.
eda performance python computer-architecture
Building an AIG Local Rewriting Engine from Scratch
How 4-cut enumeration, truth-table matching, and NPN equivalence classes achieve 13.8% area reduction on ICCAD benchmarks — without calling any EDA APIs.
eda algorithm python deep-dive
EDA Logic Synthesis Engine
A from-scratch DAG-aware synthesis engine for the ICCAD 2026 CADC Contest, featuring AIG rewriting, bit-parallel simulation, and LLM-assisted exploration.
project eda python algorithm
Infrastructure as Code: A Hardware Engineer's Approach to Web Dev
Applying RTL design philosophies — zero bloat, strict resource management, and maximum throughput — to build a Lighthouse-100 personal portfolio using Astro & WebGL.
infrastructure performance three.js devops
Infrastructure for EDA Automation: Securing a Linux Verification Server
How I built a production-ready, secure Linux cluster environment for LLM-driven EDA verification using Docker rootless mode, cgroups, and strict UFW policies.
infrastructure eda docker security
Docker Container Security: Beyond the Basics
Rootless Docker, cgroups limits, read-only filesystems, and network policies — how to run containers without becoming the next CVE headline.
docker security containers devops